A Novell High-speed low-power domino logic technique for static output in evaluation phase for high frequency inputs
نویسندگان
چکیده
Domino logic is widely used for high switching speed and high performance circuits. In dynamic logic, problem arises while cascading one gate to another. In order to cascade dynamic logic, domino logic is used which consists of an inverter used between two stages. Robustness of domino logic diminishes with downscaling as leakage power increases. This paper presents a new proposed domino logic circuit with improved speed. Present work proposed domino logic scheme which gives static output also in evaluation phase with high frequency inputs which other domino techniques do not support. This proposed circuit is designed by making use of modified keeper circuitry. The proposed circuit has low powerdelay product as compared to other domino logic circuits. All the circuits have been simulated in cadence virtuoso 180nm technology. According to simulations, the circuit shows much better performance as compared to conventional domino logic circuits. Keywords— Domino logic; dynamic gates; evaluation phase; precharge phase; static gates.
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